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Development of dynamic tool PID/PWP limits to achieve product defect density goal

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2 Author(s)
Jacobson, L. ; Nat. Semicond. Corp., South Portland, ME, USA ; Hua Su

Summary form only given. Prediction of integrated circuit manufacturing yield has become the main application of developed yield models. In this paper, a different application, which is to develop tool PID/PWP limits to achieve product defect density goal, is shown. The developed limits are dynamic as most elements, such as defect size distribution, killer pareto and kill ratio change and improve from time to time. This method can be used to monitor any product yield enhancement activity in a consistent manner

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI

Date of Conference:

10-12 Sep 1997