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Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

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6 Author(s)
Chia-Tsen Dai ; Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Po-Yen Chiu ; Ming-Dou Ker ; Fu-Yi Tsai
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The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

Published in:

Physical and Failure Analysis of Integrated Circuits (IPFA), 2012 19th IEEE International Symposium on the

Date of Conference:

2-6 July 2012