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This paper demonstrates electrical degradation due to hot carrier injection (HCI) stress for devices with different bend gate structures by three-dimensional (3D) TCAD simulation. The amount and distribution of Si/SiO2 interface trap under different stress conditions were also evaluated by 3D simulation for the first time. Trap-related models were employed to perform accurate physics phenomena during the HCI stress test. Compared with conventional strip gate device, device with bend gate structure suffer from higher interface trap generation after stress, leading to worse on-state resistance (RON) and drain current degradations.