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Block-Based CS in a CMOS Image Sensor

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3 Author(s)
Dadkhah, M. ; Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada ; Deen Jamal, M. ; Shirani, S.

An implementation of the compressive sensing (CS) method with a CMOS image sensor is presented. The conventional three-transistor active pixel sensor (APS) structure and switched capacitor circuits are exploited to develop an analog implementation of the CS encoding in a CMOS sensor. With the analog implementation, the sensing and encoding are performed in the same time interval and making a real-time encoding process to optimize the frame rate of the imager. A block readout strategy is proposed to capture the required CS measurements for different blocks of the image, rather than the common column-row readout method. All measurement circuits are placed outside the array by this readout strategy, and the imager becomes scalable for larger array sizes. Because there is no extra in-pixel element for the CS measurement process, the fill factor of the imager is the same as its corresponding APS imager without CS. The proposed structure is designed and fabricated in 0.13-μm CMOS technology for a 2 × 2 array. The experimental results confirm the validity of the design in making monotonic and appropriate CS measurements. The functionality of the block readout method and the scalability of the imager are confirmed by fabrication of a 4×4 block and a 16×16 array.

Published in:

Sensors Journal, IEEE  (Volume:14 ,  Issue: 8 )