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3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of TSVs in a 3-D IC such that the yield of the 3-D IC is boosted. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3-D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.