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Strain technology has become indispensable for present CMOS integrated circuits (ICs) as the feature size of transistor shrinks. In the meantime, stress-induced variation has also become an unavoidable problem. Unintentional stress, such as shallow trench isolation (STI)- induced stress, is one of the main variation sources and is strongly layout dependent. In this paper, a new 2-D layout-dependent STI stress model and related device parameter model are proposed. The stress model captures layout parameters along both the longitudinal direction and the transverse direction, based on which channel stress induced by STI is derived. Device parameters including threshold voltage, mobility, and saturation velocity are then modified according to several analytical models. The model can be integrated into standard CMOS IC design flow. By comparing with TCAD simulation and experiments with 65-nm process, it shows that the new model can give a better prediction accuracy than the original process design kit.