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Accurate timing transfer and recovery over packet networks (IP, Ethernet, MPLS, etc.) has become an important requirement for delivering many telecommunication services. This requirement stems from the fact that current networks are migrating from time-division multiplexing (TDM) technologies to packet based ones, and also the need to synchronize the many timing-dependent devices like TDM access devices and wireless base stations. Unlike TDM, packet networks are asynchronous by design and do not have embedded timing transfer capabilities. Differential clocking is used when there is a network interface with its own reference source clock (the service clock) and there is the need to transfer this clock over a core packet network (with its own independent reference network clock) to another interface. The network clock serves as a sampling clock for the service clock. Timing transfer and recovery over a packet network is a networked control problem given the difficulty in making the recovered clock at the remote location compliant with strict telecom standards. In this paper, we describe the architecture, servo algorithm, and phase-locked loop (PLL) of a method for implementing differential clock recovery over packet networks. The technique involves a clock source or transmitter sending counter values to a receiver from a counter that is clocked and reset, respectively, by the service clock and network clock. It is general enough to be applied in a wide variety of packet networks such IP, MPLS, Ethernet, etc.