By Topic

Two ESD Detection Circuits for 3x VDD-Tolerant I/O Buffer in Low-Voltage CMOS Processes With Low Leakage Currents

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hongxia Liu ; Key Lab. of Minist. of Educ. for Wide Band-Gap Semicond. Mater. & Devices, Xidian Univ., Xi'an, China ; Zhaonian Yang ; Qingqing Zhuo

Two novel 3×VDD-tolerant electrostatic discharge (ESD) protection circuits using only low-voltage devices without extra power consumption are proposed for 0.18- μm 1.8-V and 90-nm 1.2-V CMOS processes, respectively. Stacked-capacitor technique and bias circuit are adopted in the two designs. The proposed ESD detection circuits can generate 36- and 38-mA currents to trigger the ESD clamp device under the ESD event. Under normal operating conditions, all the devices are free from the gate-oxide reliability threat. The leakage currents of the 0.18- μm and 90-nm circuits are 0.9 and 200 nA under 3×VDD, respectively. The simulation results show that both the circuits can be successfully used for 3×VDD-tolerant I/O buffers.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:13 ,  Issue: 1 )