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In this paper, a space vector pulsewidth modulation (PWM) (SVPWM) algorithm is proposed, which is in α'β' frame with dc-link capacitor voltage equalization for diode-clamped multilevel converters (DCMCs). The α'β' frame is a coordinate system similar to the αβ frame. In this frame, some original complex calculations are substituted by integer additions, integer subtractions, truncations, etc. It brings the time and area efficiency to fixed-point digital realization, particularly for the application in a field-programmable gate array. Meanwhile, a minimum energy property of multiple dc-link capacitors is applied as the basic principle for voltage equalization based on a capacitor current prediction algorithm. By evaluating the redundant vectors in each pulse dwelling period, the balancing algorithm chooses an optimal vector, generates the optimal PWM signals, and sustains the voltage stability. After that, an arbitrary multilevel SVPWM intellectual property core is designed and analyzed in the α'β' frame. At the end of this paper, a five-level DCMC-based static synchronous compensator is built and tested. The experimental results verify the balancing algorithm and the system steady-state and dynamic performances.
Date of Publication: May 2013