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Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method

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3 Author(s)
F. Fummi ; Dipartimento di Elettronica, Politecnico di Milano, Italy ; D. Sciuto ; M. Serra

This paper presents a mixed approach for sequential circuit test pattern generation employing the accuracy of structural algorithms and the speed of a pattern generator working at the functional level. The new strategy selects from the State Transition Graph of a Finite State Machine the appropriate edges that allow a functional test pattern generator (FSMTest) to build test sequences covering 100% of the detectable single stuck-at and gate-delay faults. Experiments and comparisons are presented to justify the proposed test strategy

Published in:

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Date of Conference:

17-19 Oct 1994