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Scheduling policies for fault tolerance in a VLSI processor

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4 Author(s)
Y. -N. Shen ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; H. Kari ; S. S. Kim ; F. Lombardi

This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the results produced by comparing the outcomes of the two versions of the same job indicates that a fault may have occurred. Several methods for appropriately scheduling the primary and secondary versions of the jobs are proposed and analyzed

Published in:

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Date of Conference:

17-19 Oct 1994