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This work presents a numerical model that allows the estimation of total ionizing dose effects in floating gate devices. The numerical model algorithm is based in a cluster of widely accepted models of the underlying physical phenomena involved in radiation effects on MOS structures. Unlike previously reported models, in addition to the trapping in the floating gate, this work considers a layer of trap centers close to the semiconductor-insulator interface. Radiation tests with FG devices integrated in a CMOS process are shown. These results are compared with computer simulations based on the proposed model.