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It has been stated that 3T1D-DRAM cell is a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by variability. In this paper, it is shown that the 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation when they are scaled to nodes smaller than 22 nm. Furthermore, we present some strategies to mitigate the cell variability. Moreover, while scaling down capacitorless DRAM cells is a challenging trend, we also show how the scaling drawbacks can be compensated through the following: 1) the channel strain of the cell devices and 2) the proposal of new strategies to further enhance the memory cell behavior.