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Algorithm-Enhanced Retention Based on Megabit Array of \hbox {Cu}_{x}\hbox {Si}_{y}\hbox {O} RRAM

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7 Author(s)
Yan-Liang Wang ; State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China ; Ya-Li Song ; Ling-Ming Yang ; Yin-Yin Lin
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Robust retention is achieved on 1-Mb CuxSiyO resistive random access memory test chip. The Ron retention fail bits can be effectively improved by enhanced set algorithm. The baking failure rate is less than 9 ppm after baking at 125°C for 1000 h under set algorithm (CC = 25 μA, PA = 2 V, and PD = 100 ns). Ron resistance can be used as retention criterion in production screening whatever the algorithm is. The mechanism of retention enhanced by algorithm is proposed based on the conductive filament model.

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Electron Device Letters, IEEE  (Volume:33 ,  Issue: 10 )