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Design of low-error fixed-width multiplier for DSP applications

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2 Author(s)
Jer Min Jou ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Shiann Rong Kuang

A low-error design of the fixed-width parallel multiplier for digital signal processing (DSF) applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit, product with lower relative product errors, but uses only about half the area of a standard parallel multiplier. These features make it very suitable for use in many DSP applications such as arithmetic coding, wavelet transformation, digital filtering

Published in:

Electronics Letters  (Volume:33 ,  Issue: 19 )