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Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design

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2 Author(s)
Seong-In Hwang ; Dept. of Inf. & Commun. Eng., Inha Univ., Incheon, South Korea ; Hanho Lee

This brief presents a method for constructing block-circulant (BC) Reed-Solomon-based low-density parity-check (RS-LDPC) codes and an efficient decoder design. The proposed construction method results in a BC form of a parity-check matrix from a random parity-check matrix for RS-LDPC codes. A decoder architecture and switch network for BC-RS-LDPC code are then developed based on the new BC parity-check matrix. Thus, an efficient decoder architecture dedicated to a promising class of high-performance BC-RS-LDPC codes is presented for the first time. Moreover, a (2048, 1723) BC-RS-LDPC decoder architecture is designed to demonstrate the efficiency of the presented techniques. Synthesis results show that the proposed decoder requires 1.3-M gates and can operate at 450 MHz to achieve a data throughput of 41 Gb/s with eight iterations.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 7 )

Date of Publication:

July 2013

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