By Topic

Charge injection error reduction circuit for switched-current systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Riffaud, P. ; Lab. d''Etudes de l''Integration des Composants et Syst., Bordeaux I Univ., Talence, France ; Tourneur, G. ; Garnier, E. ; Roux, P.

The authors propose a novel circuit for reducing the charge injection error based on the technique of current source replication, applied to a second generation memory cell. Using the proposed circuit, offset error, linear gain error, and total harmonic distortion are significantly reduced to the detriment of the occupied die area and the power dissipation which are multiplied by a factor of three

Published in:

Electronics Letters  (Volume:33 ,  Issue: 20 )