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Boostable Repeater Design for Variation Resilience in VLSI Interconnects

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2 Author(s)
Kyu-Nam Shim ; Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA ; Jiang Hu

Process variations and circuit aging continue to be one of the main challenges to the power-efficiency of VLSI circuits, as a considerable power budget must be allocated to cushion timing variations. A design-time allocation implies uniform power consumption on all fabricated instances, even if many instances do not have strong variations. Adaptive design provides a power-efficient approach to variation tolerance, since it uses power only when the variations of a circuit instance are harmful. This paper is an effort toward supply voltage adaptation for variation resilience in VLSI interconnects. The main idea is a boostable repeater design that can transiently and autonomously raise its internal voltage rail to boost switching speed. The boosting can be turned on/off to compensate variations. The boostable repeater design achieves fine-grained voltage adaptation without stand-alone voltage regulators or an additional power grid. Since interconnect is a widely recognized cause of bottleneck in chip performance, and tremendous repeaters are employed on chip designs, boostable repeater has plenty of chances to improve system robustness. Experimental results indicate that our approach significantly outperforms existing techniques, including over-design, conventional adaptive supply voltage system, and online adjustable buffer.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:21 ,  Issue: 9 )