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A 64–84-GHz PLL With Low Phase Noise in an 80-GHz SiGe HBT Technology

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3 Author(s)
Gang Liu ; Inst. of Electron Devices & Circuits & the Competence Center on Integrated Circuits in Commun., Ulm Univ., Ulm, Germany ; Trasser, A. ; Schumacher, H.

This paper presents a 64-84-GHz phase-locked loop (PLL) realized in a low-cost 80-GHz HBT technology. The circuit consists of a wide tuning-range voltage-controlled oscillator, a push-push frequency doubler, a divide-by-32 frequency divider, a phase detector and an active loop filter. The measured phase noise at 1-MHz offset is -106 dBc/Hz. The output power is -2.5 dBm at 64 GHz, and it slowly decreases to -8.1 dBm at 84 GHz, with a maximum dc power consumption of 517 mW. To the authors' knowledge, the circuit achieves the widest frequency tuning range and its in-band phase noise is the lowest among the fully integrated V/W-band PLLs reported to date.

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Microwave Theory and Techniques, IEEE Transactions on  (Volume:60 ,  Issue: 12 )