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We study mixed-mode stress degradation in SiGe HBTs using a novel physical TCAD model in which the processes of hot carrier generation within the semiconductor, carrier propagation to the oxide interface, and formation of interface traps are directly modeled. Transient degradation simulations using a calibrated 2-D SiGe HBT model correlate well with measured data. With this novel simulation tool, we investigate the bias dependence and location of interface traps and show that secondary holes produced by impact ionization are the dominant carrier to damage the emitter-base (EB) spacer oxide interface, confirming previously reported results. We also compare in detail trap formation at the EB spacer and shallow-trench-isolation (STI) oxide interfaces as a function of time and stress condition. At the STI oxide interfaces, we find that hot electrons and holes each dominate trap formation in different regions, and the hot carriers that reach the STI predominately originate outside of the selectively implanted collector, revealing the important role played by dopant diffusion from the extrinsic base of quasi-self-aligned SiGe HBTs.