Efficient decimation filters for ΣΔ ADCs, using new FIR filters involving shift s and only two additions

A new class of digital FIR filters with application to the decimation filter design for ΣΔ Analog to Digital Converters (ADCs) is introduced, which can be realized using an efficient multiplier-less structure. The filter coefficients are conditioned in such a way that, independent of the order, the realization structure comprises shifts (delays) and only two additions; hence the proposed filters have close relation to the first order Cascaded Integrator-Comb (CIC) filters, but offering more design parameters to overcome their limited degree of freedom. A filter Involving Shifts and Only Two Additions (abbreviated as ISOTA), has coefficients dependant to each other; this together with the non-linearity of the discrete-space of the coefficients, makes the design procedure somewhat limited. A simple design method is used to find the desired solutions, based on applying gradient search algorithm to the possible combinations of the coefficients (obtained by state tree diagram). Demonstrative examples as well as the practical application are presented.