Performance enhancement of a 10-Bit 50-MS/s open loop pipelined ADC using a novel digital calibration

In this paper, a 10-bit 50-Msample/s pipelined ADC by using dynamic charge injection technique is presented. By the proposed scheme, the input voltage range is increased and power consumption is reduced. For the calibration of the output codes, a new method is presented which uses polynomial inverse function. By the use of the inverse function and simultaneously adjustment of both the weights of stages and coefficients of polynomials, linearity is achieved. The proposed ADC is designed and simulated in a 90-nm CMOS technology. Simulation results show that the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 59 dB, a peak spurious-free dynamic range (SFDR) of 72.5 dB. The ADC's power consumption (without calibration circuitry) is 1 mW (without calibration circuitry).