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Clearing the clutter: Unified modeling and verification methodology for system level hardware design

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2 Author(s)
Watanabe, Y. ; Cadence Design Syst., Berkeley, CA, USA ; Swan, S.

The state-of-the-art design practice for complex SoCs employs multiple models of hardware components with different use cases. The cost of building and maintaining those models is high, and verifying the consistency among those models is time consuming. This paper highlights needs and issues of creating these models, and presents emerging approaches for developing solutions to address the issues.

Published in:

Formal Methods and Models for Codesign (MEMOCODE), 2012 10th IEEE/ACM International Conference on

Date of Conference:

16-17 July 2012