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A 3–5 GHz LNA in 0.25µm SOI CMOS process for implantable WBANs

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3 Author(s)
Iji, A. ; Dept. of Electron. Eng., Macquarie Univ., Sydney, NSW, Australia ; Xi Zhu ; Heimlich, M.

A low-voltage, low-power single-ended LNA is implemented in a 0.25 μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs.

Published in:

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Date of Conference:

5-8 Aug. 2012