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This paper explores a common-emitter buffer-based frequency multiplier which can be applied to the phase-locked loop (PLL) to boost the overall output frequency and locking range by locking the PLL in a lower fundamental frequency and then multiplying the fundamental frequency to a higher output frequency. An integer PLL with a frequency quadrupler is designed to verify this technique in 130nm SiGe BiCMOS technology. The post-layout simulation shows this D-band (110-170GHz) PLL has a wide locking range from 126.9 to 132.4GHz. The output power into a 50Ω load is -30dBm. The total power consumption is approximately 16.95mW. The PLL phase noise at 1MHz offset frequency is -66dBc/Hz. Its settling time is ~2μs. The microchip area is 850μm×760μm.