By Topic

Design of 0.45V,1.3mW ultra high gain CMOS LNA using gm-boosting and forward body biasing technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Dehqan, A. ; Microelectron. Lab., Sadjad Inst. for Higher Educ., Mashhad, Iran ; Kargaran, E. ; Mafinezhad, Khalil ; Nabovati, Hooman

Two fully integrated low noise amplifiers using gm-boosting technique for ultra-low voltage and ultra-low-power GPS applications are designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNAs can operate at reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 17.6 dB with a noise figure of 3 dB, while consuming only 1.1mW dc power with an ultra low supply voltage of 0.45 V. A gm-boosting technique is used to increase the LNA gain and reduce noise figure at the cost of a little circuit power consumption. For the LNA with a gm-boosting technique, a remarkable gain of 20.8 dB gain is achieved with a dc power of 1.3 mW and noise figure 2.9dB. The supply voltage figure of merit(FOM1) and the tuning-range figure of merit(FOM2) are optimal at 46.22 dB/V and 9.61(v.mw)-1 for gm-boosting technique, respectively.

Published in:

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Date of Conference:

5-8 Aug. 2012