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Design of 0.45V,1.3mW ultra high gain CMOS LNA using gm-boosting and forward body biasing technique

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4 Author(s)
Dehqan, A. ; Microelectron. Lab., Sadjad Inst. for Higher Educ., Mashhad, Iran ; Kargaran, E. ; Mafinezhad, Khalil ; Nabovati, Hooman

Two fully integrated low noise amplifiers using gm-boosting technique for ultra-low voltage and ultra-low-power GPS applications are designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNAs can operate at reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 17.6 dB with a noise figure of 3 dB, while consuming only 1.1mW dc power with an ultra low supply voltage of 0.45 V. A gm-boosting technique is used to increase the LNA gain and reduce noise figure at the cost of a little circuit power consumption. For the LNA with a gm-boosting technique, a remarkable gain of 20.8 dB gain is achieved with a dc power of 1.3 mW and noise figure 2.9dB. The supply voltage figure of merit(FOM1) and the tuning-range figure of merit(FOM2) are optimal at 46.22 dB/V and 9.61( for gm-boosting technique, respectively.

Published in:

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Date of Conference:

5-8 Aug. 2012