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Advancement of VLSI technology helps semiconductor industry to manufacture Through-silicon-via (TSV) based 3D stacked ICs (SICs). During 3D assembly, multiple partial stack tests are necessary. In this paper, we address test architecture optimization for 3D stacked ICs implemented with hard dies. We consider two different test sets and derive optimal solutions to minimize over all test time when complete stack and multiple partial stacks, need to be tested. Results are performed for two handcrafted 3D SICs comprising of various SoCs from ITC'02 SoC test benchmarks. In this work we consider the test architecture optimization for 3D SIC where the die level test architecture is fixed and each die consists of one SoC. We show that decrease in total test length with the increasing number of test pins is more than increase in the number of test TSVs. Furthermore, we also present test schedules and corresponding test lengths for every multiple insertions.