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This paper presents a design methodology considering both INWE (Inverse-Narrow-Width-Effect) and RSCE (Reverse-Short-Channel-Effect) by sizing transistor's width and length accordingly to achieve close-to-most energy-efficient digital circuit design. By using a fitted and modified INWE-aware, RSCE-aware and variation-aware model, fast estimation of width, length and nf for optimum finger can be obtained. Using such method, EDP (Energy-Delay Product) optimized gates for low-power cell library in a commercial 180nm CMOS process are developed. The proposed finger-based gates have the FO4 Delay and EDP reduced by 44%~72% and 31%~76% respectively compared with conventionally sized library gates.