Skip to Main Content
In this paper, we present a 0.2-1.8-GHz digital-intensive receiver front-end using a voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) running at 1.4 Gs/s in 90-nm CMOS. To improve the out-of-band rejection, we propose a second-order anti-aliasing Sinc filter that can be embedded in the ADC, which exploits the integrating nature of a VCO. the nonideal effect of the proposed architecture is analyzed with regard to the waveform imperfection due to device mismatch. The proposed receiver achieves -94 dBm of sensitivity at 1-MHz bandwidth and - 6.8 dBm of IIP3, while providing 50-dB rejection of aliased signals.
Microwave Theory and Techniques, IEEE Transactions on (Volume:60 , Issue: 10 )
Date of Publication: Oct. 2012