By Topic

An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Daeyun Kim ; Department of Semiconductor Science, University of Dongguk, Seoul, Korea ; Minkyu Song

Many kinds of wide-dynamic-range (DR) CMOS image sensors (CIS) have been developed, such as a multiple sampling, a multiple exposure technique, etc. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this brief, a new digital logarithmic single-slope analog-to-digital converter (SS-ADC) with a digital counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the logarithmic SS-ADC enhances the DR by 24 dB. The proposed ADC, which has been fabricated using a 0.13- μm CIS process, achieves a signal-to-noise-plus-distortion ratio of 57.6 dB at 50 kS/s.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 10 )