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An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC

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2 Author(s)
Daeyun Kim ; Dept. of Semicond. Sci., Univ. of Dongguk, Seoul, South Korea ; Minkyu Song

Many kinds of wide-dynamic-range (DR) CMOS image sensors (CIS) have been developed, such as a multiple sampling, a multiple exposure technique, etc. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this brief, a new digital logarithmic single-slope analog-to-digital converter (SS-ADC) with a digital counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the logarithmic SS-ADC enhances the DR by 24 dB. The proposed ADC, which has been fabricated using a 0.13- μm CIS process, achieves a signal-to-noise-plus-distortion ratio of 57.6 dB at 50 kS/s.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 10 )

Date of Publication:

Oct. 2012

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