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Techniques to improve decoded video quality for erroneous H.264 bit streams in an asynchronous multiprocessor architecture

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2 Author(s)
Resmi Rajendran ; Video Signal Processing, Texas Instruments India Pvt. Ltd., Bangalore, 560093, India ; Pavan Shastry

A conventional synchronous single processor decoder system can no longer cater to the demands of the market in terms of processing speed. A modern asynchronous multiprocessor architecture partitions the decoding functions into different processing cores so that real time decoding of high mega pixel streams is achieved by parallel execution. The number of processor cores is a balance between chip area, processing Mhz requirements and the latency incurred in the pipeline. Error handling on a modern asynchronous multiprocessor architecture is far more involved compared to its synchronous counterparts. This paper presents a software design and methodology in order to achieve better error resilience and concealment quality in a High Profile H.264 Universal Decoder on an asynchronous multiprocessor architecture. It involves robust error handling and error recovery, detection and handling of possible start code overrun, overcoming limitations due to the extremely efficient software design, improved error detection logic, and improvements in End of Picture Detection. Average PSNR improvement of 0.35 dB and maximum 4 dB has been obtained by these techniques, when tested on an error stream test suite of more than 100 randomly corrupted streams.

Published in:

2012 International Conference on Signal Processing and Communications (SPCOM)

Date of Conference:

22-25 July 2012