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Fast generation of statistically-based worst-case modeling of on-chip interconnect

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5 Author(s)
N. Chang ; Hewlett-Packard Co., Palo Alto, CA, USA ; V. Kanevsky ; O. S. Nakagawa ; K. Rahmat
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In this paper, we describe a novel methodology for obtaining statistically-based worst case (i.e. 3-σ) R (resistance), C (capacitance), and delay given variations in interconnect-related process parameters. Our approach is based on a weighted root-sum square method to derive 3-σ C. A Monte Carlo-based method is used for the generation of 3-σ R as well as randomized distributed RC nets to obtain realistic 3-σ delays for long interconnect nets such as global critical paths. Using this methodology for a long critical net analysis on a 0.35 μm process, a more than 70% improvement in 3-σ delay estimation compared with the traditional skew-corner worst case delay can be realized

Published in:

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Date of Conference:

12-15 Oct 1997