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ADDLL for Clock-Deskew Buffer in High-Performance SoCs

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4 Author(s)
Jung-Hyun Park ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Dong-Hoon Jung ; Kyungho Ryu ; Seong-Ook Jung

In this brief, we propose an all-digital delay locked loop (ADDLL) for a clock-deskew buffer. A low static phase offset at a high operating frequency is achieved by adopting a high-resolution window phase detector (PD) and a tristate-inverter-based ladder type coarse delay line (CDL). The proposed PD generates a high-resolution detection window that is adaptive to the process-voltage-temperature variation and reduces the static phase offset to nearly half of the fine delay line (FDL) resolution using a dual-output FDL. A proposed CDL is adopted in order to attain a small coarse delay step using tristate-inverters. The proposed ADDLL is designed using 0.13- μm process technology with a supply voltage of 1.2 V. The operating frequency range is 700 MHz to 2.0 GHz. The maximum static phase offset is less than 14.75 ps at all conditions and the power consumption is 4.0 mW at 2.0 GHz.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 7 )

Date of Publication:

July 2013

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