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A data alignment technique for improving cache performance

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4 Author(s)
Ranjan Panda, P. ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Nakamura, H. ; Dutt, N.D. ; Nicolau, A.

We address the problem of improving the data cache performance of numerical applications-specifically, those with blocked (or tiled) loops. We present DAT, a data alignment technique utilizing array-padding, to improve program performance through minimizing cache conflict misses. We describe algorithms for selecting tile sizes for maximizing data cache utilization, and computing pad sizes for eliminating self-interference conflicts in the chosen tile. We also present a generalization of the technique to handle applications with several tiled arrays. Our experimental results comparing our technique with previous published approaches on machines with different cache configurations show consistently good performance on several benchmark programs, for a variety of problem sizes

Published in:

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Date of Conference:

12-15 Oct 1997