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TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model

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8 Author(s)
Takamura, A. ; Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan ; Kuwako, M. ; Imai, M. ; Fujii, T.
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Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3 MIPS using the Dhrystone V2.1 benchmark

Published in:

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Date of Conference:

12-15 Oct 1997

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