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Design and implementation of MPEG-2/DVB scrambler unit and VLSI chip

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3 Author(s)
Won-Ho Kim ; Satellite Commun. Div., ETRI, Taejon, South Korea ; Kyung-Jae Chen ; Hyun-Suk Cho

This paper describes the MPEG-2/DVB scrambler unit (DVB-SU) and VLSI chip developed for ETRI's conditional access system (CAS) for a digital broadcasting system. The DVB-SU is designed and implemented based on an ASIC, FPGAs and a DSP. The ASIC, compliant with the EP-DVB common scrambling specification, is a 128-pin MQFP type and operates with a 50 MHz system clock; it has features of flexible conditional access handling and interfaces with a commercial MPEG-2 multiplexer in compliance with the MPEG-2 system specification (ISO/IEC 13818). It has been integrated as a part of a conditional access sub-system for a digital broadcasting system and conforms so that it meets all the initial objectives and performance requirements

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Consumer Electronics, IEEE Transactions on  (Volume:43 ,  Issue: 3 )