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Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping

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4 Author(s)
Sasidhar, N. ; Oregon State Univ., Corvallis, OR, USA ; Gubbins, D. ; Hanumolu, P.K. ; Moon, U.

In this brief, a design technique for high-speed pipelined analog-to-digital converters (ADCs) that enables processing rail-to-rail input swing without the use of dual set of reference voltages is proposed. The scheme not only operates on a single set of power supplies but also helps in power reduction in the ADC using a new multistage signal mapping technique aided by asynchronous sub-ADC quantization. To further reduce both power and area, an asynchronous successive approximation register ADC backend is used. To demonstrate the efficacy of the proposed techniques, a 1.2-V 10-bit 125-MS/s ADC is designed in a 90-nm CMOS process, and simulation results are presented.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 9 )