By Topic

Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Naga Sasidhar ; Mobius Semiconductor, Irvine, USA ; David Gubbins ; Pavan Kumar Hanumolu ; Un-Ku Moon

In this brief, a design technique for high-speed pipelined analog-to-digital converters (ADCs) that enables processing rail-to-rail input swing without the use of dual set of reference voltages is proposed. The scheme not only operates on a single set of power supplies but also helps in power reduction in the ADC using a new multistage signal mapping technique aided by asynchronous sub-ADC quantization. To further reduce both power and area, an asynchronous successive approximation register ADC backend is used. To demonstrate the efficacy of the proposed techniques, a 1.2-V 10-bit 125-MS/s ADC is designed in a 90-nm CMOS process, and simulation results are presented.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 9 )