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In this brief, a design technique for high-speed pipelined analog-to-digital converters (ADCs) that enables processing rail-to-rail input swing without the use of dual set of reference voltages is proposed. The scheme not only operates on a single set of power supplies but also helps in power reduction in the ADC using a new multistage signal mapping technique aided by asynchronous sub-ADC quantization. To further reduce both power and area, an asynchronous successive approximation register ADC backend is used. To demonstrate the efficacy of the proposed techniques, a 1.2-V 10-bit 125-MS/s ADC is designed in a 90-nm CMOS process, and simulation results are presented.