By Topic

A display processor conforming to all DTV formats with 188-tap FIR filters and 284 Kb FIFO memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Hosotanl, S. ; LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Yazawa, M. ; Matsuo, N. ; Sugawa, S.
more authors

To achieve a single chip solution for a display processor conforming to all DTV formats, various hardwired approaches such as the write end toggle signal (WETS) based design technique and dynamic voltage sensing FIFO architecture have been developed. As a result, all functions including macroblock-to-raster conversion, frame/filed rate conversion, scan format conversion, and ordinary picture making functions such as color interpolation, enhancement, inverse matrix, on screen display, and D/A conversion have been successfully integrated into a single chip. The display processor has a total memory capacity of 284 Kb and filters with a total of 188 taps in an area of 14.9 mm×14.9 mm. It was fabricated in 0.5 um CMOS technology with 2-metal

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:43 ,  Issue: 3 )