Skip to Main Content
Low-voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high holding voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the holding voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the holding voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V.