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A variable length coding ASIC chip for HDTV video encoders

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4 Author(s)
Jin-Young Yang ; Electron. & Telecommun. Res. Inst., South Korea ; Youngsun Lee ; Hankyu Lee ; Jinwoong Kim

This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a stand-alone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0.8 μm CMOS gate array technology, and runs at 27 MHz clock rate

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Consumer Electronics, IEEE Transactions on  (Volume:43 ,  Issue: 3 )