A variable length coding ASIC chip for HDTV video encoders

This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a stand-alone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0.8 /spl mu/m CMOS gate array technology, and runs at 27 MHz clock rate.