Optimal automatic hardware synthesis for signal processing algorithms

This paper presents a complete methodology for the automatic synthesis of VLSI architectures used in digital signal processing. Most signal processing algorithms have the form of an n-dimensional nested loop with unit uniform loop carried dependencies. We model such algorithms with generalized UET grids. We calculate the optimal makespan for the generalized UET grids and then we establish the minimum number of systolic cells required for achieving the optimal makespan. We present a complete methodology for the hardware synthesis of the resulting architecture, based on VHDL. This methodology automatically detects all necessary computation and communication elements and produces optimal layouts. The complexity of our proposed scheduling policy is completely independent of the size of the nested loop and depends only on its dimension, thus being the most efficient (in terms of complexity) known to us. All these methods were implemented and incorporated in an integrated software package which provides the designer with a powerful parallel design environment, from high level signal processing algorithmic specifications to low-level (i.e., actual layouts) optimal implementation. The evaluation was performed using well-known algorithms from signal processing.