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Efficient implementation of MPEG video codec using dual processors

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3 Author(s)
V. Sankar ; Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India ; S. Srinivasan ; S. R. Rangarajan

Presented here is a parallel processing system based on a digital signal processor (DSP) and a PC-AT host processor to increase the computational speed of the MPEG compression algorithm. The algorithm is split into independent tasks of approximately the same complexity, allocated to the DSP and the host processor based on the relative merits of the tasks, and computed concurrently, resulting in a twofold increase in speed. Furthermore, a provision is made to enable the user to effect a compression-quality tradeoff

Published in:

Digital Signal Processing Proceedings, 1997. DSP 97., 1997 13th International Conference on  (Volume:2 )

Date of Conference:

2-4 Jul 1997