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A comment on “An analytical model for designing memory hierarchies”

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4 Author(s)
Jacob, B.L. ; Dept. of Electr. Eng., Michigan Univ., Ann Arbor, MI, USA ; Chen, P.M. ; Mudge, T.N. ; Silverman, S.R.

In our paper, “An analytical model for designing memory hierarchies” (see ibid., vol. 45, no. 10, p. 180-1, 194 (1996)), we made the following statement: “Failing to apply a specific model of workload locality makes it impossible to provide an easily used, closed-form solution for the optimal cache configuration, and so the results from these papers have contained dependencies on the cache configuration-the number of levels, or the sizes and hit rates of the levels.” Our description did not accurately reflect the contents of the paper by J.E. MacDonald and K.L. Sigworth (1975), and we regret any false impressions caused by the inaccuracy

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Computers, IEEE Transactions on  (Volume:46 ,  Issue: 10 )