By Topic

Low-level error recovery mechanism for self-checking sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Favalli, M. ; Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy ; Metra, C.

To match the reliability requirements of small embedded systems, a design methodology is proposed that provides some fault tolerant capabilities to self-checking sequential circuits. By means of simple modifications, such circuits are made fault tolerant with respect to transient, crosstalk and delay faults, while they maintain their self-checking capabilities with respect to permanent faults. The method requires a small area overhead and may also provide some benefit from the yield point of view

Published in:

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Date of Conference:

20-22 Oct 1997