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Generation and verification of tests for analogue circuits subject to process parameter deviations

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4 Author(s)
Spinks, S.J. ; Dept. of Electron. Eng., Hull Univ., UK ; Chalk, C.D. ; Bell, I.M. ; Zwolinski, M.

The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower

Published in:

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Date of Conference:

20-22 Oct 1997