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Application of a yield model merging critical areas and defectivity to industrial products

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2 Author(s)
S. Levasseur ; Central R&D, SGS-Thomson Microelectron., Crolles, France ; F. Duvivier

This paper reports a yield model merging critical areas computed by a survey sampling based estimation tool (EYES) and a large set of defectivity measurements performed during the fabrication process at the SGS-Thomson Crolles plant. This model is applied to commercial devices processed in a mature 0.5 μ technology. The robustness of the model was tested with a large number of lots including multiple products, process versions (routes) and defectivity variations

Published in:

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Date of Conference:

20-22 Oct 1997