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Optimizing Option Pricing Algorithms and Profiling Power Consumption on VLIW APU Architecture

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3 Author(s)
Doerksen, M. ; Dept. of Comput. Sci., Univ. of Manitoba, Winnipeg, MB, Canada ; Thulasiraman, P. ; Thulasiram, R.K.

Heterogeneous multi-core architectures have become an integral component of high performance systems and high performance scientific computing (HPC). The use of these systems has been vital for research applications but until recently have not been a factor in the consumer level experience. However, with new technologies such as AMD's Accelerated Processing Unit (APU) which combines the Central Processing Unit and Graphics Processing Unit onto a single die, consumers now have an affordable high performance system at their disposal. AMD's APUs are aimed at providing good performance and low power consumption for all markets. Financial applications can benefit from this heterogeneous architecture for real time processing. However, to obtain good performance, algorithms must be coded to efficiently utilize the APU architecture. In this paper, we have optimized two option pricing algorithms on the APU making use of vectorization and loop unrolling for improved performance. Our algorithms are tested on both an ATI Mobility Radeon 5870 and an AMD E-350 APU which use the VLIW5 architecture. We also study the power consumption of these architectures to determine how they compare to traditional CPU- and GPU- based systems.

Published in:

Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on

Date of Conference:

10-13 July 2012