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Multistack optimization for data-path chip layout

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2 Author(s)
Luk, W.K. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Dean, A.A.

A special multistack structure and optimization technique to partition, place, and wire the data-path macros in the form of the multistack structure are described, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: to fit the circuits within the chip boundary; to ensure data-path internal wirability; as well as external stack wirability to the other circuits; and to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high-density data path chips

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 1 )

Date of Publication:

Jan 1991

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